An embodiment of the present invention relates to the field of integrated circuits, and, more particularly, to diodes for electrostatic discharge (ESD) protection.
Integrated circuit inputs are frequently protected against ESD by dual diodes D1 and D2 as shown in FIG. 1. The diodes D1 and D2 are set up as shown so that one or the other will forward bias, nondestructively, and keep the voltage of the signal that is provided to an input buffer 105, low enough to avoid damaging the input buffer. As shown, if the polarity of an ESD event is positive, the diode D2 will route the current associated with the ESD event to the supply voltage Vcc and if the polarity of the ESD event is negative, the diode D1 will route the current to Vss.
Currently, the layouts for protection diodes such as D1 and D2 of FIG. 1 have been designed to maximize the efficiency of the diodes as conductors of ESD current. This typically means full metallization and contacting of diode stripes, locating p+ and n+ diode stripes as near as possible to each other, and generous use of vertical metal 2 (M2) (or other higher level metal layer) to connect the horizontal metal 1 (M1) (or lower level metal layer) together to reduce the series resistance of the diodes as shown in an exemplary layout of FIG. 2. A typical goal of the diode layout is to maximize the density of the diode stripes to achieve high ESD protection per unit area.